The present invention is related to testing of logic circuit designs and, in particular, to compaction of test response data.
Testing of complicated digital logic circuits requires the analysis of a large amount of test response data. A variety of output compaction techniques have been devised for reducing the size of test response data stored in test memory. Techniques to reduce output responses can be classified into two basic categories: “spatial compaction” and “temporal compaction.” Spatial compaction reduces response data volume by reducing the number of outputs that are observed by automatic test equipment. Temporal compaction compresses output responses over a period of time into a signature, which is typically significantly smaller than the size of even a single uncompressed output response.
The output response of scan test patterns unfortunately can contain what are referred to as “unknown” values. This can occur for several reasons: the presence of non-scan flip-flops, embedded memories, tristate buffers, the limitation in accuracy of simulation, etc. The presence of unknown values in the output response creates complications for test data reduction. Consider, for example, a simple spatial compactor built with XOR trees. If an output that has a fault effect appears along with an unknown at a given scan shift cycle, the fault effect is masked and cannot be observed at the output of the compactor during that cycle. Consider a multiple input signature register, the simplest and most popular example of a temporal compactor. The entrance of any known value corrupts the signature for output responses over the entire period of time. Thus, the presence of unknown values at outputs is catastrophic in temporal compaction. Since it is difficult and costly to eliminate all unknown sources from the design, it is preferable that the output response compaction technique take into account the presence of unknown values in scan flip-flops. For example, blocking logic (based on OR gates or AND gates) can be used to block unknown values before they enter into a temporal compactor. If an unknown value is scanned out at a shift cycle, the unknown value can be blocked by a logic gate which is driven by a control signal generator. Control data for the blocking logic, unfortunately, needs to be stored like test data, typically in the automatic test equipment. Accordingly, it would be advantageous to minimize the control data volume while avoiding any significant reduction in the observability of the compactor.